Three-dimensional semiconductor memory device
US8497533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2012 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Jul 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.