Package substrates and semiconductor packages having the same
US8497569B2 · kind B2 · utility
0Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2011 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Apr 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83385
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.