Semiconductor packaging method and structure thereof
US8497579B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Feb 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/9211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.