Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US8497587B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Sep 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.