Integrated circuit elementary cell with a low sensitivity to external disturbances
US8497701B2 · kind B2 · utility
2Cited by
6References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00338
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.