Solid-state memory cell with improved read stability
US8498143B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2011 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Jul 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid-state memory in which stability assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an isolation gate connected between one of the storage nodes and the input of the opposite inverter. The isolation gate may be realized by complementary MOS transistors connected in parallel, and receiving complementary isolation control signals. In read cycles, or in unselected columns during write cycles, the isolation gate is turned off slightly before the word line is energized, and turned on at or after the word line is de-energized. By isolating the input of one inverted from the opposite storage node, the feedback loop of the cross-coupled inverters is broken, reducing the likelihood of a cell stability failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.