Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling
US8498152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2010 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Jun 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.