Method of fabricating gate and method of manufacturing semiconductor device using the same
US8501550B2 · kind B2 · utility
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1References
11Claims
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Key dates
| Filing date | Sep 21, 2011 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Dec 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.