Stacked integrated chips and methods of fabrication thereof
US8501587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2009 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Nov 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.