Semiconductor structure and method for slimming spacer
US8502288B2 · kind B2 · utility
7Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2011 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | May 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.