Self-aligned two-step STI formation through dummy poly removal
US8502316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Jan 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.