Semiconductor device packages with solder joint enhancement element and related methods
US8502363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2012 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Mar 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.