Stack package structure and fabrication method thereof
US8502370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2012 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Aug 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package structure is provided, including: a substrate; an insulating layer formed on the substrate and having openings for exposing die attach pads and conductive pads of the substrate, respectively; a plurality of first and second conductive terminals formed on the insulating layer and electrically connected to the die attach pads and the conductive pads, respectively; a dielectric layer formed on the insulating layer and having a cavity for exposing the first conductive terminals and a plurality of openings exposing the second conductive terminals; copper pillars formed respectively in the openings of the dielectric layer; a semiconductor chip disposed in the cavity and electrically connected to the first conductive terminals; solder balls formed respectively on the copper pillars that are located proximate to the die attach area; and a package structure disposed on and electrically connected to the solder balls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.