Patent · US Active

Device with a data retention mode and a data processing mode

US8502585B2 · kind B2 · utility

5Cited by

4References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Kuenemund · Munich, DE
Anton Huber · Burghausen, DE
Roswitha Deppe · Munich, DE

Key dates

Filing date	Jul 21, 2011
Grant date	Aug 6, 2013
Priority date	—
Expiry date	Sep 7, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/356156
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A device includes a flip flop and a control circuit. The flip flop includes a flip flop data input terminal and a flip flop clock input terminal. The control circuit includes a control circuit data input terminal and a control circuit clock input terminal. The control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.