Semiconductor memory device and programming method thereof
US8503232B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.