Column command buffer and latency circuit including the same
US8503256B2 · kind B2 · utility
3Cited by
4References
17Claims
0Family size
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Inventor
Key dates
| Filing date | Jul 21, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.