Low power LDPC decoding under defects/erasures/puncturing
US8504887B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Oct 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6362
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This disclosure relates generally to low power data decoding, and more particularly to low power data decoders for use under defects, erasures, and puncturing, with a low density parity check (LDPC) encoder. Systems and methods are disclosed for decoding a vector with punctured, detected defect and/or erased bits. Systems and methods are also disclosed for decoding a vector with undetected defects and/or unknown error patterns. Low power decoding may be performed in an LDPC decoder during the process of decoding an LDPC code in the case of defects, erasures, and puncturing. The low power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes, or the devices that make use of low power LDPC decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.