Standard cells having flexible layout architecture/boundaries
US8504972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Oct 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.