Reducing data read latency in a network communications processor architecture
US8505013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Oct 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/2441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.