BEOL anti-fuse structures for gate last semiconductor devices
US8507326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2011 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Jan 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.