Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates
US8507365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2009 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Dec 1, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a′) that is related to the substrate lattice parameter (a). The lattice parameter (a′) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.