Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
US8508971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2011 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Feb 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.