Phase locked loop device and method thereof
US8509370B2 · kind B2 · utility
3Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2009 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Jun 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0805
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.