Data processing system having peripheral-paced DMA transfer and method therefor
US8510482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2010 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | May 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system having a processor, a DMA controller, a peripheral, and a memory, a method includes initiating a DMA transfer between the peripheral and the memory, wherein the DMA transfer comprises N subsets of data to be transferred between the peripheral and the memory, N having a value of two or more; asserting, by the peripheral, an event status indicator each time an event is completed by the peripheral; in response to each assertion of the event status indicator, the peripheral, based on a data request enable signal from the DMA controller, performing one of asserting a data request signal provided to the DMA controller or providing an interrupt request to the processor; and in response to each assertion of the data request signal, the DMA controller initiating transfer of a next subset of data of the N subsets of data between the memory and the peripheral.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.