Performance driven layout optimization using morphing of a basis set of representative layouts
US8510699B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for generating variants of a circuit layout and evaluating quality of the variants are provided. In one aspect, a method for generating at least one variant layout for a cell design includes the following steps. At least a first basis layout and a second basis layout are obtained for the cell design, each having a plurality of shapes, each of the shapes being a polygon having a plurality of sides and vertices. One or more of the shapes in the first basis layout are linked with one or more of the shapes in the second basis layout that represent a common feature of the cell design resulting in a plurality of linked shapes. Starting with either the first basis layout or the second basis layout, a location of the vertices of each of the linked shapes are changed to produce the variant layout for the cell design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.