Chemical mechanical planarization processes for fabrication of FinFET devices
US8513127B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 25, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Oct 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.