Fin field effect transistor with variable channel thickness for threshold voltage tuning
US8513131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Jun 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.