Signal repowering chip for 3-dimensional integrated circuit
US8513663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2010 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Dec 31, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.