Multi-protocol gearbox
US8514634B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Nov 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can include write circuitry configured to implement a write finite state machine selected from a plurality of write finite state machines and read circuitry configured to implement a read finite state machine selected from a plurality of read finite state machines. The system also can include a multi-port memory having a write port controlled by the write circuitry and a read port controlled by the read circuitry. The write circuitry and the read circuitry can be configured to implement the selected write finite state machine and the selected read finite state machine to perform one of a plurality of different data transformations using the multi-port memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.