Thread synchronization in a multi-thread network communications processor architecture
US8514874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Jul 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/2441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate a thread of contexts for each task received by the packet classifier from a plurality of processing modules of the network processor. The scheduler includes one or more output queues to temporarily store contexts. Each thread corresponds to an order of instructions applied to the corresponding packet, and includes an identifier of a corresponding one of the output queues. The scheduler sends the contexts to a multi-thread instruction engine that processes the threads. An arbiter selects one of the output queues in order to provide output packets to the multi-thread instruction engine, the output packets associated with a corresponding thread of contexts. Each output queue transmits output packets corresponding to a given thread contiguously in the order in which the threads started.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.