Implementing storage adapter performance optimization with enhanced hardware and software interface
US8516164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | May 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.