Bandwidth-efficient directory-based coherence protocol
US8516199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2009 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Apr 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.