Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus
US8516231B2 · kind B2 · utility
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5References
12Claims
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Key dates
| Filing date | Jan 28, 2010 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | May 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.