Error correcting code protected quasi-static bit communication on a high-speed bus
US8516338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2012 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Jun 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.