Real-time error detection by inverse processing
US8516356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2010 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.