Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts
US8516407B1 · kind B1 · utility
7Cited by
3References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 30, 2012 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Jan 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.