Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model
US8516420B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2007 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Aug 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.