Wafer-to-wafer process for manufacturing a stacked structure
US8518741B1 · kind B1 · utility
13Cited by
2References
25Claims
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Key dates
| Filing date | Nov 7, 2012 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Nov 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.