Assembly method for three dimensional integrated circuit
US8518753B2 · kind B2 · utility
29Cited by
55References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Nov 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.