Fabricating method of semiconductor device
US8518772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Jun 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabricating method of a semiconductor device includes forming an interlayer insulation layer on a substrate, the interlayer insulation layer including a storage node contact plug, forming an etch stop layer on the interlayer insulation layer, the etch stop layer including a silicon layer or a silicon germanium layer, forming a molding insulation layer on the etch stop layer, forming a hole in the molding insulation layer by selectively etching the molding insulation layer until a portion of the etch stop layer is exposed, forming a first conductive layer conformally on an inner surface of the hole and on a top surface of the molding insulation layer, and forming a metal silicide pattern in a predetermined area of the etch stop layer exposed by the molding insulation layer by annealing the first conductive layer and the etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.