Through wafer vias and method of making same
US8518787B2 · kind B2 · utility
9Cited by
36References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2012 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Sep 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.