Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8519436B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 19, 2012 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Nov 19, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/547
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.