Chip stacking structure and fabricating method of the chip stacking structure
US8519524B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2012 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Aug 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.