Patent · US Active

Clock glitch detection

US8519768B2 · kind B2 · utility

2Cited by

17References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Markus Baumeister · Aachen, DE
Joachim Kruecken · Munich, DE
Rolf Dieter Schlagenhaft · Poing, DE

Key dates

Filing date	Mar 31, 2009
Grant date	Aug 27, 2013
Priority date	—
Expiry date	May 27, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.