Methods and apparatus for receiving high and low voltage signals using a low supply voltage technology
US8519771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for receiving high voltage signals using a receiver designed in a low supply voltage technology are disclosed. One embodiment of an integrated circuit includes a single ended driver including an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor. An input pass gate is coupled to the single ended driver, and is configured as a PMOS pass gate coupled in parallel with the NMOS transistor in the single ended driver. In a low voltage mode, the NMOS transistor and the PMOS pass gate form a first pass gate for transmitting the input signal to the receiver. In a high voltage mode, the PMOS pass gate is disabled, and the NMOS transistor and PMOS transistor form a second pass gate for transmitting the input signal to the receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.