Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor
US8521993B2 · kind B2 · utility
3Cited by
8References
4Claims
0Family size
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Key dates
| Filing date | Apr 9, 2007 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Oct 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.