Inventor · Hillsboro, OR, US

Alexandre J. Farcy

30Patents
4h-index
42Co-inventors
59Inventor score

Filing activity: Dec 29, 2003 → Aug 30, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US10409612B2 Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution Physics 7 Active
US8549264B2 Add instructions to add three source operands Physics 6 Active
US8738893B2 Add instructions to add three source operands Physics 4 Active
US7797683B2 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor Physics 4 Active
US8521993B2 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Physics 3 Active
US9164762B2 Rotate instructions that complete execution without reading carry flag Physics 2 Active
US9940130B2 Rotate instructions that complete execution either without writing or reading flags Physics 2 Active
US9916160B2 Rotate instructions that complete execution either without writing or reading flags Physics 2 Active
US8504807B2 Rotate instructions that complete execution without reading carry flag Physics 2 Active
US8438369B2 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Physics 2 Active
US9940131B2 Rotate instructions that complete execution either without writing or reading flags Physics 2 Active
US9354875B2 Enhanced loop streaming detector to drive logic optimization Emerging Cross-Sectional Technologies 1 Active
US11106461B2 Rotate instructions that complete execution either without writing or reading flags Physics 1 Active
US9990201B2 Multiplication instruction for which execution completes without writing a carry flag Physics 1 Active
US9280492B2 System and method for a load instruction with code conversion having access permissions to indicate failure of load content from registers Physics 1 Active
US8402253B2 Managing multiple threads in a single pipeline Physics 1 Active
US7913064B2 Operation frame filtering, building, and execution Physics 1 Active
US7533247B2 Operation frame filtering, building, and execution Physics 1 Active
US8825989B2 Technique to perform three-source operations Physics 0 Active
US11900108B2 Rotate instructions that complete execution either without writing or reading flags Physics 0 Active
US8589663B2 Technique to perform three-source operations Physics 0 Active
US10649774B2 Multiplication instruction for which execution completes without writing a carry flag Physics 0 Active
US8504804B2 Managing multiple threads in a single pipeline Physics 0 Active
US7475225B2 Method and apparatus for microarchitecture partitioning of execution clusters Physics 0 Expired
US9158696B2 Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.