Spatial correlation-based estimation of yield of integrated circuits
US8522173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2012 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Aug 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.