Clustered stacked vias for reliable electronic substrates
US8522430B2 · kind B2 · utility
32Cited by
7References
8Claims
0Family size
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Key dates
| Filing date | Jul 14, 2012 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Jul 14, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49222
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.