Method of manufacturing semiconductor package
US8524539B2 · kind B2 · utility
8Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2011 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Dec 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.